In a data processing system having a synchronous bus, memory and I/O addresses are transmitted over the bus during clocked bus cycles. There is a time delay between the start of a bus cycle and when address signals being placed on the bus become valid, which is known as the "address delay time". Logic which interfaces to a synchronous bus usually performs an address decode in one of two ways. The address signals from the bus are either decoded directly without being latched or such signals are first latched by the receiving device and then decoded. The choice of implementation is driven by factors such as frequency of operation and address delay time. Direct unlatched decoding is often chosen since unlatched decoded addresses are available earlier than latched decoded addresses. However, if the decoded addresses are fed to other synchronous logic, e.g., a state machine, the decoding time must be less than the time of the clock period minus the address delay time. If the addresses are first latched before being fed to other clocked logic, the address decoding time is extended by one full clock period. A decoder is comprised of combinational logic, and the decoder path delay is determined by the technology and the number of levels of logic. Since decoding time is often a critical timing parameter and may be quite complex, the unlatched method of address decode limits the operational frequency of the logic.
In the known prior art, an address decoder was designed to operate in only one way dependent upon its technology and system operational frequency. While latched decoding could be used for both slow and fast systems, its use in a slow system might degrade performance. On the other hand, unlatched decoding is faster in slow systems but cannot be used in fast systems. The invention is designed to overcome such limitations of the prior art by providing an address decoder operable to decode addresses selectively in either one of two modes, latched or unlatched, and thereby allow the decoder to be used in an optimal fashion over a wide range of operational frequencies.
The closest known patents are U.S. Pat. Nos. 4,750,839-Wang et al and 4,766,572-Kobayashi. U.S. Pat. No. 4,750,839 is entitled a "SEMICONDUCTOR MEMORY WITH STATIC COLUMN DECODE AND PAGE MODE ADDRESSING CAPABILITY", and discloses circuitry for either latching a column address before it is decoded or transmitting an unlatched column address directly to a decoder. Selection of whether the address is to be latched is not dependent on operational speed but upon the order in which a row address strobe and a column address strobe are received. U.S. Pat. No. 4,766,572 is entitled a "SEMICONDUCTOR MEMORY HAVING A BYPASSABLE DATA OUTPUT LATCH". Such latch is selectively settable to determined whether the data read from memory is latched or not. Such teaching does not deal with decoding addresses.